devices incorporated 1 l7c185 8k x 8 static ram (low power) 07/07/1999Clds.185-e 64k static rams features description l7c185 8k x 8 static ram (low power) devices incorporated q q q q q 8k x 8 static ram with chip select powerdown, output enable q q q q q auto-powerdown? design q q q q q advanced cmos technology q q q q q high speed to 12 ns maximum q q q q q low power operation active: 425 mw typical at 25 ns standby (typical): 400w (l7c185) 200 w (l7c185-l) q q q q q data retention at 2 v for battery backup operation q q q q q desc smd no. 5962-38294 q q q q q available 100% screened to mil-std-883, class b q q q q q plug compatible with idt7164, cypress cy7c185/186 q q q q q package styles available: ? 28-pin plastic dip ? 28-pin ceramic dip ? 28-pin plastic soj ? 28-pin ceramic flatpack ? 28-pin ceramic lcc ? 32-pin ceramic lcc the l7c185 is a high-performance, low-power cmos static ram. the storage circuitry is organized as 8,192 words by 8 bits per word. the 8 data in and data out signals share i/o pins. these devices are available in four speeds with maximum access times from 12 ns to 25 ns. inputs and outputs are ttl compat- ible. operation is from a single +5 v power supply. power consumption for the l7c185 is 425 mw (typical) at 25 ns. dissipation drops to 60 mw (typical) for the l7c185 and 50 mw (typical) for the l7c185-l when the memory is deselected. two standby modes are available. proprietary auto-powerdown? circuitry reduces power consumption automatically during read or write accesses which are longer than the minimum access time, or when the memory is deselected. in addition, data may be retained in inactive storage with a supply voltage as low as 2 v. the l7c185 and l7cl185-l consume only 30 w and 15 w (typical) respectively at 3 v, allowing effective battery backup operation. the l7c185 provides asynchronous (unclocked) operation with matching access and cycle times. two chip enables (one active-low) and a three- state i/o bus with a separate output enable control simplify the connection of several chips for increased storage capacity. memory locations are specified on address pins a 0 through a 12 . read- ing from a designated location is accomplished by presenting an address and driving ce 1 and oe low, and ce 2 and we high. the data in the addressed memory location will then appear on the data out pins within one access time. the output pins stay in a high-impedance state when ce 1 or oe is high, or ce 2 or we is low. writing to an addressed location is accomplished when the active-low ce 1 and we inputs are both low, and ce 2 is high. any of these signals may be used to terminate the write operation. data in and data out signals have the same polarity. latchup and static discharge pro- tection are provided on-chip. the l7c185 can withstand an injection current of up to 200 ma on any pin without damage. l7c185 b lock d iagram row address column select & column sense row select i/o 7-0 5 column address 256 x 32 x 8 memory array 8 8 we control ce 2 oe ce 1 obsolete
devices incorporated l7c185 8k x 8 static ram (low power) 2 64k static rams 07/07/1999Clds.185-e l7c185- symbol parameter test condition 20 15 12 10 unit i cc1 v cc current, active (note 6) 125 130 140 150 ma m aximum r atings above which useful life may be impaired (notes 1, 2) storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ........................................................................................ C3. 0 v to +7.0 v signal applied to high impedance output ............................................................................... C3.0 v to +7.0 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 200 ma o perating c onditions to meet specified electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.5 v v cc 5.5 v active operation, industrial C40c to +85c 4.5 v v cc 5.5 v active operation, military C55c to +125c 4.5 v v cc 5.5 v data retention, commercial 0c to +70c 2.0 v v cc 5.5 v data retention, industrial C40c to +85c 2.0 v v cc 5.5 v data retention, military C55c to +125c 2.0 v v cc 5.5 v l7c185 symbol parameter test condition min typ max unit v oh output high voltage v cc = 4.5 v, i oh = C4.0 ma 2.4 v v ol output low voltage i ol = 8.0 ma 0.4 v v ih input high voltage 2.2 v cc v +0.5 v il input low voltage (note 3) C0.5 0.8 v i ix input leakage current ground v in v cc C5 + 5a i oz output leakage current (note 4) C5 + 5a i cc2 v cc current, ttl inactive (note 7) 12 40 ma i cc3 v cc current, cmos standby (note 8) 80 2000 a i cc4 v cc current, data retention v cc = 3.0 v (note 9) 10 150 a c in input capacitance ambient temp = 25c, v cc = 5.0 v 7 pf c out output capacitance test frequency = 1 mhz (note 10) 8pf e lectrical c haracteristics over operating conditions (note 5) obsolete
devices incorporated 3 l7c185 8k x 8 static ram (low power) 07/07/1999Clds.185-e 64k static rams l7c185C 20 15 12 10 symbol parameter min max min max min max min max t avav read cycle time 20 15 12 10 t avqv address valid to output valid (notes 13, 14) 20 15 12 10 t axqx address change to output change 3 3 3 3 t clqv chip enable low to output valid (notes 13, 15) 20 15 12 10 t clqz chip enable low to output low z (notes 20, 21) 3333 t chqz chip enable high to output high z (notes 20, 21) 8433 t olqv output enable low to output valid 10 7 6 5 t olqz output enable low to output low z (notes 20, 21) 0000 t ohqz output enable high to output high z (notes 20, 21) 8433 t pu input transition to power up (notes 10, 19) 0000 t pd power up to power down (notes 10, 19) 20 15 12 10 t chvl chip enable high to data retention (note 10) 0000 switching characteristics over operating range r ead c ycle notes 5, 11, 12, 22, 23, 24 (ns) previous data valid data valid address data out t avav i cc t pd t avqv t axqx t pu 4.5 v data retention mode 4.5 v ce v cc t chvl t avav v ih v ih 3 2 v r ead c ycle a ddress c ontrolled notes 13, 14 r ead c ycle ce/oe c ontrolled notes 13, 15 d ata r etention note 9 high impedance data valid high impedance data out 50% 50% t pu i cc oe t olqz t pd t avav t ohqz t chqz t olqv t clqz t clqv ce obsolete
devices incorporated l7c185 8k x 8 static ram (low power) 4 64k static rams 07/07/1999Clds.185-e switching characteristics over operating range l7c185C 20 15 12 10 symbol parameter min max min max min max min max t avav write cycle time 20 15 12 10 t clew chip enable low to end of write cycle 15 12 10 9 t avbw address valid to beginning of write cycle 0 0 0 0 t avew address valid to end of write cycle 15 12 10 9 t ewax end of write cycle to address change 0 0 0 0 t wlew write enable low to end of write cycle 15 11 9 8 t dvew data valid to end of write cycle 10 8 6 5 t ewdx end of write cycle to data change 0 0 0 0 t whqz write enable high to output low z (notes 20, 21) 0333 t wlqz write enable low to output high z (notes 20, 21) 7555 w rite c ycle notes 5, 11, 12, 22, 23, 24 (ns) w rite c ycle we c ontrolled notes 16, 17, 18, 19 w rite c ycle ce c ontrolled notes 16, 17, 18, 19 data-in valid address data in high impedance t avbw we t avav t clew t avew t wlew t dvew t ewdx t ewax t pd t pu ce i cc data out data-in valid high impedance address data out data in t pd ce i cc we t wlqz t pu t pu t dvew t ewdx t whqz t ewax t wlew t avew t clew t avbw t avav obsolete
devices incorporated 5 l7c185 8k x 8 static ram (low power) 07/07/1999Clds.185-e 64k static rams notes +5 v output r 1 480 w 30 pf r 2 255 w including jig and scope 11. test conditions assume input transition times of less than 3 ns, reference levels of 1.5 v, output loading for specified i ol and i oh plus 30 pf (fig. 1a), and input pulse levels of 0 to 3.0 v (fig. 2). 12. each parameter is shown as a minimum or maximum value. input requirements are specified from the point of view of the exter- nal system driving the chip. for example, t avew is specified as a minimum since the external system must supply at least that much time to meet the worst-case require- ments of all parts. responses from the inter- nal circuitry are specified from the point of view of the device. access time, for ex- ample, is specified as a maximum since worst-case operation of any device always provides data within that time. 13. we is high for the read cycle. 14. the chip is continuously selected ( ce 1 low, ce 2 high). 15. all address lines are valid prior-to or coincident-with the ce 1 and ce 2 transition to active. 16. the internal write cycle of the memory is defined by the overlap of ce 1 and ce 2 active and we low. all three signals must be active to initiate a write. any signal can terminate a write by going inactive. the address, data, and control input setup and hold times should be referenced to the sig- nal that becomes active last or becomes inac- tive first. 17. if we goes low before or concurrent with the latter of ce 1 and ce 2 going active, the output remains in a high impedance state. 18. if ce 1 and ce 2 goes inactive before or concurrent with we going high, the output remains in a high impedance state. 19. powerup from i cc2 to i cc1 occurs as a result of any of the following conditions: a. rising edge of ce 2 (ce 1 active) or the falling edge of ce 1 (ce 2 active). b. falling edge of we (ce 1 , ce 2 active). c. transition on any address line (ce 1 , ce 2 active). d. transition on any data line (ce 1 , ce 2 , and we active). the device automatically powers down from i cc1 to i cc2 after t pd has elapsed from any of the prior conditions. this means that power dissipation is dependent on only cycle rate, and is not on chip select pulse width. 1. maximum ratings indicate stress specifi- cations only. functional operation of these products at values beyond those indicated in the operating conditions table is not implied. exposure to maximum rating con- ditions for extended periods may affect re- liability of the tested device. 2. the products described by this specifica- tion include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive elec- trical stress values. 3. this product provides hard clamping of transient undershoot. input levels below ground will be clamped beginning at C0.6 v. a current in excess of 100 ma is required to reach C2.0 v. the device can withstand in- definite operation with inputs as low as C3 v subject only to power dissipation and bond wire fusing constraints. 4. tested with gnd v out v cc . the de- vice is disabled, i.e., ce 1 = v cc , ce 2 = gnd. 5. a series of normalized curves is available to supply the designer with typical dc and ac parametric information for logic devices static rams. these curves may be used to determine device characteristics at various temperatures and voltage levels. 6. tested with all address and data inputs changing at the maximum cycle rate. the device is continuously enabled for writing, i.e., ce 1 v il , ce 2 3 v ih , we v il . input pulse levels are 0 to 3.0 v. 7. tested with outputs open and all address and data inputs changing at the maximum read cycle rate. the device is continuously disabled, i.e., ce 1 3 v ih , ce 2 v il . 8. tested with outputs open and all ad- dress and data inputs stable. the device is continuously disabled, i.e., ce 1 = v cc , ce 2 = gnd. input levels are within 0.2 v of v cc or gnd. 9. data retention operation requires that v cc never drop below 2.0 v. ce 1 must be 3 v cc C 0.2 v or ce 2 must be 0.2 v. all other inputs must meet v in 3 v cc C 0.2 v or v in 0.2 v to ensure full powerdown. for low power version (if applicable), this re- quirement applies only to ce 1 , ce 2 , and we; there are no restrictions on data and address. 10. these parameters are guaranteed but not 100% tested. 20. at any given temperature and voltage condition, output disable time is less than output enable time for any given device. 21. transition is measured 200 mv from steady state voltage with specified loading in fig. 1b. this parameter is sampled and not 100% tested. 22. all address timings are referenced from the last valid address line to the first transi- tioning address line. 23. ce 1 , ce 2 , or we must be inactive during address transitions. 24. this product is a very high speed device and care must be taken during testing in order to realize valid test information. in- adequate attention to setups and proce- dures can cause a good part to be rejected as faulty. long high inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes di- rectly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper terminations must be used. f igure 1a. <3 ns gnd +3.0 v 90% 10% 90% 10% <3 ns f igure 2. +5 v output 5 pf including jig and scope r 1 480 w r 2 255 w f igure 1b. obsolete
devices incorporated l7c185 8k x 8 static ram (low power) 6 64k static rams 07/07/1999Clds.185-e 28-pin 0.3" wide 28-pin 0.6" wide *the low power version is specified by adding the "l" suffix after the speed grade (e.g., l7c185cmb15l) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 gnd v cc we ce 2 a 8 a 9 a 11 oe a 10 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 gnd v cc we ce 2 a 8 a 9 a 11 oe a 10 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 ordering information 0c to +70c c ommercial s creening C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening C40c to +85c c ommercial s creening plastic dip (p10) l7c185pc15* l7c185pc12* l7c185pc10* l7c185pi15* l7c185pi12* plastic dip (p9) l7c185nc15* l7c185nc12* l7c185nc10* l7c185ni15* l7c185ni12* l7c185ni10* speed 15 ns 12 ns 10 ns 15 ns 12 ns 10 ns 20 ns 15 ns 12 ns 20 ns 15 ns 12 ns ceramic dip (c6) l7c185ic15* l7c185ic12* l7c185ic10* l7c185im20* L7C185IM15* l7c185im12* l7c185imb20* l7c185imb15* l7c185imb12* ceramic dip (c5) l7c185cc15* l7c185cc12* l7c185cc10* l7c185cm20* l7c185cm15* l7c185cm12* l7c185cmb20* l7c185cmb15* l7c185cmb12* l7c185pi10* obsolete
devices incorporated 7 l7c185 8k x 8 static ram (low power) 07/07/1999Clds.185-e 64k static rams 28-pin 0.3" wide 28-pin *the low power version is specified by adding the "l" suffix after the speed grade (e.g., l7c185mmb15l) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we ce 2 a 8 a 9 a 11 oe a 10 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 nc a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 gnd v cc we ce 2 a 8 a 9 a 11 oe a 10 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 ordering information 0c to +70c c ommercial s creening C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening C40c to +85c c ommercial s creening speed 15 ns 12 ns 10 ns 15 ns 12 ns 10 ns 20 ns 15 ns 12 ns 20 ns 15 ns 12 ns ceramic flatpack (m2) l7c185mc15* l7c185mc12* l7c185mc10* l7c185mm20* l7c185mm15* l7c185mm12* l7c185mmb20* l7c185mmb15* l7c185mmb12* plastic soj (w2) l7c185wc15* l7c185wc12* l7c185wc10* l7c185wi15* l7c185wi12* l7c185wi10* obsolete
devices incorporated l7c185 8k x 8 static ram (low power) 8 64k static rams 07/07/1999Clds.185-e 28-pin 32-pin *the low power version is specified by adding the "l" suffix after the speed grade (e.g., l7c185kmb15l) 4 5 6 7 8 9 10 11 12 26 25 24 23 22 21 20 19 18 top view 13 3 27 228 1 14 15 16 17 ce 2 a 8 a 9 a 11 oe a 10 ce 1 i/o 7 i/o 6 nc a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 gnd i/o 3 i/o 4 i/o 5 a 6 a 7 a 12 v cc we 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 30 top view 31 14 19 20 4 32 31 2 15 16 17 18 a 8 a 9 a 11 nc oe a 10 ce 1 i/o 7 i/o 6 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 i/o 1 i/o 2 gnd nc i/o 3 i/o 4 i/o 5 a 7 a 12 nc nc v cc we ce 2 ordering information 0c to +70c c ommercial s creening C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening C40c to +85c c ommercial s creening speed 15 ns 12 ns 10 ns 15 ns 12 ns 10 ns 20 ns 15 ns 12 ns 20 ns 15 ns 12 ns ceramic leadless chip carrier (k5) l7c185kc15* l7c185kc12* l7c185kc10* l7c185km20* l7c185km15* l7c185km12* l7c185kmb20* l7c185kmb15* l7c185kmb12* ceramic leadless chip carrier (k7) l7c185tc15* l7c185tc12* l7c185tc10* l7c185tm20* l7c185tm15* l7c185tm12* l7c185tmb20* l7c185tmb15* l7c185tmb12* obsolete
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